The VLSI (very large scale integration) circuits used in computers and other electronic systems or subsystems typically employ a large number of circuit elements. [As used herein, "circuit elements" is intended to generically include active as well as passive devices or components of any kind used in electronic or electro-optical applications.] VLSI circuits may at present have many thousands to over a million transistors on a single die, the semiconductor chip from which the circuit is fabricated, and a computer system may have large numbers of such chips. The technology continues to move in the direction of increasing device density for primarily two interrelated reasons. One is the need to reduce the size of the circuits in order to permit increased complexity for a given machine size with reduced manufacturing cost and power requirements. The other is the need to increase the operating speeds. The electromagnetic propagation delay or transit time of signals traveling within the machine between circuit elements, and particularly between different integrated circuits, is a significant factor in limiting the operating speed. Therefore, it is desirable that integrated circuit chips of a machine which communicate with one another be placed as closely together as possible.
A serious constraint in the increase of packing density of integrated circuits is their thermal management; i.e., the ability to effectively carry away the heat generated by the electronic components. The density of heat generating devices and their operating frequency (since the power dissipation of some types of circuits increases with frequency) both contribute to the problem of heat generation. In the 2-dimensional case, to make the interconnect propagation delays a constant fraction of a clock cycle, the power density tends to increase as the cube of the operating clock frequency. If the high power densities are not counterbalanced by improved heat removal, higher device operating temperatures will result which will drastically increase the failure rate of electronic integrated circuits or, if high enough, cause the circuits to be inoperative, or even cause permanent destruction of the circuit. In general, the build-up of heat can be controlled by incorporating a high thermal conductance, called a heat sink, between the integrated circuit chips and some cooling medium suited to the demands of the particular application. The cooling medium may be air, water, a common refrigerant, or even liquid nitrogen. It is possible to incorporate the heat sink within the circuit board or substrate material on which the circuit chips are mounted in some applications, providing the heat sink material is good enough to effectively support the lateral heat flow through the substrate. The effectiveness of the heat sink is a function of the thermal conductivity of the heat sink material, so materials of high thermal conductivity are preferred for use as heat sinks. Diamond has the highest thermal conductivity (k=2000 W/m degree K. at 300 degrees K.) of any known material. Silver, copper and aluminum (with k=430, 400 and 240, respectively at 300 degrees K.) are among the best cheaper alternative heat sink materials, but are electrical conductors, requiring special electrical insulating steps if isolated conductors must be passed through the material, compromising the thermal conductance. Also, silver and copper (which are better thermal conductors than aluminum) are much heavier per unit volume than diamond. A further advantage of diamond is that its thermal expansion coefficient is a better match to that of silicon than most other heat sinking materials. Diamond has been suggested and used as a heat sink material for electronic devices and circuits because of its superior thermal conductivity and insulating properties, but its practical use has been limited by its cost/benefit ratio in circuit applications where alternative heat sinking materials may be more readily provided in the necessary sizes and shapes, and where such alternate materials are operationally adequate.
In recent years it has been demonstrated that there can be great advantages in a 3-dimensional interconnected packaging approach, wherein a number of 2-dimensional circuit boards (each typically containing many chips) are stacked vertically and wherein, instead of being edge connected, vertical interconnects between the boards are provided and are distributed over the area of the boards. Such an approach has the advantage of reducing the maximum path lengths and electromagnetic propagation delays of the signal interconnection lines in the overall circuit and in greatly reducing the critical path delays for signals among smaller groups of chips implementing key functions, as well as generally making available much higher levels of system connectivity. Notwithstanding these advantages, a serious problem of the 3-dimensional interconnect packaging approach is the amount of heat that builds up as a consequence of the high density of devices and the smaller external surface area per unit volume or per integrated circuit of the 3-dimensional package. Sophisticated heat removal techniques, including the pumping of cooling fluid through a number of paths in the structure and/or immersion of the structure in a refrigerant which may be pumped through the structure, are expensive and/or inconvenient, particularly due to the presence of the conductive vertical interconnects between boards which tends to block the spaces between the boards that would otherwise be available as flow paths for the cooling fluid (e.g., air, fluorinert, etc.).
It is among the objects of the present invention to provide improved electronic circuit fabrication, interconnection, packaging, and thermal management which is responsive to the described problems and limitations of the prior art.